The present invention relates generally to memories, and more specifically, to the erase of a non-volatile memory.
The erase of a non-volatile memory cell is significant in many characteristics of the memory. A typical erase in floating gate devices is Fowler-Nordheim tunneling (FNT). This does require higher voltages than the normal operating voltages, which in turn requires that the peripheral circuits be larger than would otherwise be required. For dielectric storage devices, SONOS (silicon-oxide-nitride-oxide-silicon) being the most common, a typical erase mechanism is hot hole injection (HHI). With dielectric storage memories, FNT erase is especially difficult to perform effectively because the erase process saturates before a sufficient level of erase has been achieved. To achieve FNT, a control gate to well voltage creates a bias voltage across the oxide immediately above the channel (bottom oxide) sufficient to cause electrons to tunnel from the nitride to the channel. This control gate to well voltage also creates a bias across the dielectric that is between the control gate and the nitride (top oxide). As the nitride is depleted of electrons the bias across the top oxide increases, eventually causing tunneling of electrons from the control electrode to the nitride through the top oxide. The electrons supplied to the nitride through the top oxide thus offsets the electrons being removed from the nitride. This is a particularly severe problem for nitride storage because the band gap of nitride is between that of oxide and silicon. Further, the electrons that can be removed are in traps in the nitride and require a higher voltage for them to pass through the oxide than for the case in which the storage element is a silicon floating gate. This saturation problem has made it very difficult to have an effective erase using FNT for dielectric storage devices.
For HHI erase, the bottom oxide must be made relatively thick because of the damage that is done to the bottom oxide by the HHI process. The greater thickness allows for this damage to occur, at least for a reasonable number of erases, without causing excessive leakage. This does ultimately effect the life of the device. The relatively thick bottom oxide results in the requirement of the larger voltages than for FNT using lesser thickness for the bottom oxide. This requirement for greater voltages results in the requirement for larger transistors in the peripheral circuitry. The larger voltages require longer gate lengths. For effective operation, the gate width to gate length ratios are important so that an increase in gate length requires a corresponding percentage increase in gate width. For example, a periphery may need to be 40 percent of the area of the memory array to meet the voltage requirements for HHI whereas a periphery for the voltages required for FNT may need to be only 20 percent of the area of the memory array. These larger device sizes also consume more power.
Thus, there is a need to have an erase of non-volatile memories that overcomes at least one and preferably more than one of these problems.